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5th International Design & Test Workshop
(IDT 2010)

December 14-16, 2010
Abu Dhabi - Yas Hotel

http://idt.adec.ac.ae

Submission Deadline Extended to October 15th, 2010!
CALL FOR PAPERS
Scope -- Submissions -- Key Dates -- Additional Information -- Committees

Scope

The International Design & Test Workshop (IDT) provides a unique forum to researchers and practitioners in the Middle East and Africa (MEA) region to come together and discuss new research ideas and present new research results in the areas of VLSI design, test, automation and fault tolerance. Workshop topics include all aspects of design, test and automation.

Specific topics are to include:

  • Analog, Mixed-Signal and RF Design and Test
  • Architectural and Logic Synthesis
  • Automatic Test Equipment
  • Built-In Self-Test (BIST)
  • Defect-Based Test
  • Design for Manufacturability (DFM)
  • Design for Reliability
  • Design for Test
  • Design of Low Power Systems and Power Analysis
  • Design Verification and Formal Methods
  • Economics of Test
  • Embedded Systems
  • Emerging Technologies, Systems and Applications
  • Failure Analysis
  • Fault Modeling
  • Fault Tolerance
  • IC Physical Design Automation
  • iDDQ and iDDT Testing
  • Memory and FPGA Test and Repair
  • MEMs Design and Test
  • Nanotechnology-based Architectures
  • On-Line Testing
  • Packaging
  • Real-time Systems
  • Reconfigurable Computing
  • Test Issues in Nanotechnology
  • SOC/NOC/MPSOC
  • Self-Repair and Design for Self-Repair
  • System Design Methods
  • System Specification and Modelling
  • Test Generation, Simulation and Diagnosis
  • Test Resource Partitioning
  • 3D IC Design and Test
  • Applications Design: Media, Signal Processing, Wireless Communication and Networking, Automotive, Military, Secure Embedded Implementations, etc.

Submissions

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To present their work at the workshop, authors are invited to submit a full paper limited to six (6) pages in the standard IEEE conference double-column format, including figures and references. Each submission should include: title, full name and affiliation of all authors, an abstract of 150 words, and keywords. It should also identify a contact author and include a complete correspondence address, phone number, fax number, and E-mail address. All submissions must be made electronically in PDF format through the IDT website. Proposals for panels, hot topic sessions and embedded tutorials are also invited.

Please ensure that your PDF file is readable by Acrobat Reader. The submission of a paper, a hot topic session or a panel proposal will be considered evidence that upon acceptance, the author(s) will register and attend in person and present the paper or organize the panel at the workshop.

Extended versions of a selection of best papers will be invited for subsequent publication in IEEE Design & Test of Computer.

Key Dates

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Submission deadline: October 15, 2010
Notification of acceptance: November 8, 2010
Final copy deadline: November 23, 2010

Additional Information
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General Information

Yervant Zorian
Virage Logic
47100 Bayside Parkway
Fremont, CA 94538, USA
Imtinan Elahi
Masdar Institute
P.O. Box 54224
Abu Dhabi, UAE


Committees
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General Co-Chairs
Y. Zorian, Virage Logic, USA
I. Elahi, Masdar Institute, UAE

Program Co-Chairs
A. Ivanov, UBC, Canada
A. Salem, Mentor Graphics, Egypt

Vice-General Co-Chairs
H. ElTahawy, Mentor Graphics, Egypt
M. Abid, CES-ENIS, Tunisia

Vice-Program Co-Chairs
A. Ossairan, E. Cowan Univ., Australia
F. Kurdahi, UC Irvine, USA

Finance Chair
W. Ali, ATIC, UAE

Publicity Co-Chairs
B. Courtois, CMP, France
J. Mohaidat, ADEC, UAE

Publications Chair
V. Beiu, UAE University, UAE

Local Arrangements Co-Chairs
H. AlSahlawy, ADEC, UAE
A. Quennarouch, ADEC, UAE
F. Abdul Jalil, ADEC, UAE

Panels Co-Chairs
S. Mourad, Santa Clara Univ, USA
A. Shihab, AUB, Lebanon
A. Shabra, Masdar Institute, UAE

Industrial Liaison Chair
M. Abadir, Freescale
M. Al Thani, Ducab, UAE
F. Al Dhaheri, Transco, UAE

IEEE Liaison
E. Bastaki, UAE

TTTC Liaison
C.-H., Chiang, Alcatel-Lucent

Web Chair
R. Mughrabi, ADEC, UA

For more information, visit us on the web at: http://idt.adec.ac.ae

The 5th International Design & Test Workshop (IDT 2010) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 1ST VICE CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

ITC GENERAL CHAIR
Gordon W. ROBERTS
McGill University
- Canada
Tel. +1-514-398-6029
E-mail gordon.roberts@mcgill.ca

TEST WEEK COORDINATOR
Yervant ZORIAN
Virage Logic Corporation - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it

 

PRESIDENT OF BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

SENIOR PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 2ND VICE CHAIR
Chen-Huan CHIANG

Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
K.T. (Tim) CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39-011-564-7055
E-mail matteo.sonzareorda@polito.it

ASIA & PACIFIC
Kazumi HATAYAMA
STARC - Japan
Tel. +
E-mail hatayama.kazumi@starc.or.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
William R. MANN
SW Test Workshop - USA
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


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